In order to improve properties of a semiconductor device, such as operation, power consumption, packing density and the like, a minimum feature size has been reduced. It is considerably technically difficult to fabricate semiconductor devices having a minimum feature size of 65 nm or less. The improvement of the properties only by miniaturization is approaching its limit.
To avoid this, a so-called strained silicon transistor has attracted attention as a transistor whose properties are improved even without miniaturization. The strained silicon transistor is a MIS transistor in which the mobility of carriers is increased by applying stress (strain) to the channel region (see, for example, Patent Documents 1 and 2). For example, in the case of a p-type MIS transistor, when compressive stress is applied in a gate length direction to the channel region of the p-type MIS transistor that is formed on a main surface of the silicon substrate having a (100) plane orientation, the mobility of positive holes increases, resulting in an increase in transistor drive capability.
Hereinafter, a method for fabricating a conventional semiconductor device having compressive stress will be described with reference to FIG. 13. FIGS. 13(a) to 13(d) are cross-sectional views showing the method for fabricating the conventional semiconductor device.
Initially, as shown in FIG. 13(a), an active region 100A is formed in an upper portion of the semiconductor substrate 100 so that the active region 100A is made of a semiconductor substrate 100 and is surrounded by isolation regions 101, and thereafter, a gate insulating film 102, a gate electrode 103 and a protective insulating film 104 are formed on the active region 100A. Thereafter, p-type extension regions 105 are formed in regions of the active region 100A each of which is located on a side of and below the gate electrode 103.
Next, as shown in FIG. 13(b), sidewalls 106 are formed on side surfaces of the gate electrode 103, and thereafter, exposed regions of the semiconductor substrate 100 are etched to desired depths. As a result, trench portions 107 are formed in regions between the sidewalls 106 and the isolation regions 101 of the active region 100A as viewed in the top.
Next, as shown in FIG. 13(c), a p-type SiGe layer 108 is epitaxially grown in the trench portions 107. Thereafter, predetermined steps are performed to complete fabrication of the conventional semiconductor device.
According to this fabrication method, it is possible to fabricate a semiconductor device including a p-type MIS transistor having the p-type SiGe layer 108 for applying compressive stress in the gate length direction to the channel region immediately blow the gate electrode 103.    Patent Document 1: U.S. Pat. No. 6,621,131    Patent Document 2: Japanese Unexamined Patent Application Publication No. 2006-13428